In the most recent École polytechnique fédérale de Lausanne (EPFL) Combinatorial Benchmark Suite, Rapid Silicon, a provider of AI and intelligent edge focused FPGAs based on open source technology, reported that its commercial open source FPGA EDA suite, Raptor, received 24 verified unique wins and two ties, 2x more wins than the leading competitor. This impressive performance in the EPFL competition is largely credited to Rapid Silicon’s “ABC-DE” algorithm, which is still pending patent protection.
Rapid Silicon is the sole FPGA vendor to compete in the EPFL benchmarking competition, breaching the long-standing tight control that FPGA firms have exercised over their EDA tools. As the first and only commercial open source FPGA design suite in the market, Raptor software from Rapid Silicon is at the forefront of the programmable revolution.
“These benchmarks are very important to the EDA community,” said Tony McDowell, director of open-source at Rapid Silicon. “Participation is growing, but the fact that Rapid Silicon is the only FPGA vendor to participate underscores our commitment to revolutionizing the FPGA industry. Even though our Raptor design software is already open source by design, including it in open benchmarking is yet another way to accelerate innovation and foster the building of a robust ecosystem for hardware developers.”
An open competition to evaluate the effectiveness of synthesis in terms of implementation size and performance is called the EPFL Combinational Benchmark Suite. In order to guarantee fairness, the EPFL releases a collection of unoptimized digital designs that are used to compare tools. The EPFL team then verifies the results.
EPFL, located in Switzerland, is one of Europe’s most prestigious science and technology universities. The EPFL Combinatorial Benchmark Suite, which was first introduced in 2015, is used to define new comparative standards for the logic optimization and synthesis community.
The latest open source benchmark suite includes approximately 20 combinational designs comprised of 10 arithmetic computational algorithms and 10 random and control designs, which are intentionally not optimized in order to test the ability of synthesis and optimization design tools. These sub-optimal designs are then synthesized to a LUT-6 architecture. The EPFL results are verified by an independent committee then published as confirmed winners.
