TIER IV joined a Japanese government initiative to develop open-source chips and toolchains optimized for Autoware and Transformer-based autonomous driving inference.
TIER IV has joined a semiconductor research programme backed by the Japan Science and Technology Agency (JST) under its Next-Generation Edge AI Semiconductor Research and Development Program. The project is led by Professor Yoshihiro Kawahara at the University of Tokyo, focusing on use-case-driven AI chip design.
TIER IV’s investors include Toyota Motor (which acquired a ~1% stake in June 2026), Sony Group, Sompo Holdings, KDDI, Suzuki Motor, and Isuzu Motors. TIER IV will develop and open-source the logic design, compiler, and related toolchain for an AI chip dedicated to end-to-end autonomous driving inference.
The chip logic is specifically designed to support Autoware, TIER IV’s open-source autonomous driving software platform, and will be evaluated as part of a software-defined System-on-Chip (SoC). The chip aims to bypass the power consumption and latency limits of general-purpose GPUs in Level 4 autonomous driving, where real-time continuous processing is required under physical AI constraints.
The hardware architecture focuses on Transformer model inference using dedicated circuits for matrix multiplication and attention calculations while minimising power draw from external memory transfers. The architecture incorporates Tensor Operator Set Architecture (TOSA) as an intermediate layer between AI models and hardware, allowing software updates to adapt to changing AI models without requiring a hardware redesign.
