Huawei opens its BiSheng Compiler foundations to global developers, bringing MLIR-based abstractions and execution model upgrades for the Ascend 950.
Huawei officially open-sourced AscendNPU IR, the intermediate representation foundation of its BiSheng Compiler, alongside Triton-Ascend. Details were presented by Huawei AscendNPU IR architect Hai Lijuan at the ninth Meet AI Compiler technical salon hosted by HyperAI on 1 August 2026. To encourage community co-construction, Huawei introduced open-source internships and task-based rewards directly on its repository homepages.
AscendNPU IR provides an MLIR-based, tile-level abstraction of Ascend hardware. It abstracts on-chip memory and data movement units, connecting downward to LLVM IR to compile Ascend binaries while allowing third-party frontends, such as Triton, to integrate upward.
The system relies on a two-layer compiler structure consisting of a hardware-independent layer and a hardware-dependent layer. The hardware-independent HFusion layer performs multi-dimensional operator fusion optimisations, whilst the hardware-dependent HIVM layer executes core mapping, processing unit mapping, and on-chip memory mapping, including fractal matrix formats for cube cores. While supporting earlier Ascend Atlas A2 and A3 architectures, the compiler extends its capabilities to the Ascend 950.
Under the Ascend 950 execution model updates, the HIVM layer expands from memory-based SIMD architectures seen in the A2 and A3 series to register-based SIMD and SIMT architectures. Cube-Vector (CV) fusion compilation transitions from exchanging data through global memory to using tightly coupled on-chip interactions. Additional compiler enhancements include refined InsertCVLoadStore analysis for control flows, MultiBuffer counters for nested loops, AutoBlockify, CV Pipeline for FlashAttention-style pipelining, and CV 1:2 splitting.
